The present invention relates, in general, to a method of fabricating a flash memory device and, more particularly, to a method of fabricating a flash memory device which can improve a hump phenomenon of a transistor formed in a peri region.
A flash memory device is a memory device in which data is retained when a supply of power is removed. The flash memory device includes a charge-trapping layer for trapping charges between the gate of a transistor and a channel in order to implement a difference in a threshold voltage Vth of the channel. The threshold voltage Vth varies depending on a state where charges are injected into the charge-trapping layer, i.e., a program state or an erased state, so that a gate voltage Vg for activating the channel is changed. The operation of the flash memory device is implemented when the threshold voltage Vth is varied depending on charges stored in the charge-trapping layer.
In a typical flash memory devices, a floating gate employing a metal layer or a polysilicon layer is used as the charge-trapping layer. In Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices, a silicon nitride layer is used as the charge-trapping layer.
In general, in the SONOS devices, a capping polysilicon layer is thickly formed on a gate insulating layer of a peri region. Therefore, if a charge-trapping layer, a blocking oxide layer and a polysilicon layer for a gate electrode of a region in which the gate of a transistor will be formed are selectively removed in the peri region, a stack type gate can be formed while preventing damage to the gate insulating layer.
However, a total height of the gate for the transistor in the peri region becomes higher than that of the cell gate in the cell region due to the thick polysilicon layer formed in the peri region. This results in the formation of a severe step between the cell region and the peri region. Consequently, after the interlayer insulating layer is deposited on the gate to form a contact plug in a subsequent process, a Self-Aligned Contact (SAC) nitride layer, which is formed on the surface of the gate in the peri region o protect the gate, is partially lost during a polishing process.
Thus, an impurity, such as hydrogen (H2), is infiltrated into the bottom of the gate of the transistor in the peri region through the lost portion of the SAC nitride layer in a subsequent process, thereby degrading the gate insulating layer. A hump phenomenon, such as the occurrence of a leakage current, occurs due to the degraded gate insulating layer. The hump on the transistor of the peri region causes well stress failure, thereby leading to a reduced yield.